| CPC G09G 3/20 (2013.01) [G11C 19/28 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0275 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/0289 (2013.01); G09G 2310/08 (2013.01); G09G 2340/0435 (2013.01); G09G 2340/16 (2013.01)] | 18 Claims |
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1. A drive control circuit, comprising:
a first control circuit, configured to acquire image data, and output a first selection command signal according to the image data; and
at least one second control circuit, each coupled to at least one scan signal line in a display panel, and coupled to the first control circuit,
wherein the at least one second control circuit is each configured to receive the first selection command signal, determine, according to the first selection command signal, a target scan signal line from among a plurality of scan signal lines in the display panel, and output a scan drive signal to the target scan signal line,
wherein the plurality of scan signal lines are divided into at least one scan signal line group each comprising at least one of the plurality of scan signal lines; the at least one second control circuit is in one-to-one correspondence with the at least one scan signal line group;
the first selection command signal comprises address information corresponding to the second control circuit coupled to the target scan signal line and data selected information corresponding to the target scan signal line;
the first control circuit is further configured to pre-store address information of the at least one second control circuit coupled to the first control circuit; and
each of the at least one second control circuit is further configured to receive the first selection command signal, and determine, according to the data selected information in the first selection command signal corresponding to the address information of the second control circuit, the target scan signal line from among the plurality of scan signal lines in the display panel,
wherein the second control circuit comprises a frame start signal control circuit and at least one first shift register unit; a drive signal output terminal of each of the at least one first shift register unit is coupled to at least one scan signal line; in the same second control circuit, the frame start signal control circuit is coupled to an input signal terminal of each of the at least one first shift register unit;
the frame start signal control circuit is configured to receive the first selection command signal, determine, according to corresponding address information and data selected information in the first selection command signal, the target scan signal line from among the correspondingly coupled scan signal line group, generate a first target frame start signal corresponding to the target scan signal line according to the determined target scan signal line, and input the generated first target frame start signal corresponding to the target scan signal line to the input signal terminal of the first shift register unit coupled to the target scan signal line; and
the first shift register unit is configured to receive the first target frame start signal corresponding to the coupled target scan signal line through the input signal terminal, and provide a clock signal input to a clock control signal terminal to the coupled target scan signal line according to the received first target frame start signal, to output the scan drive signal to the target scan signal line.
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