US 12,475,400 B2
Input/output systems and methods for superconducting devices
Kelly T.R. Boothby, Vancouver (CA)
Assigned to D-WAVE SYSTEMS INC., Burnaby (CA)
Filed by D-WAVE SYSTEMS INC., Burnaby (CA)
Filed on Jun. 6, 2024, as Appl. No. 18/735,514.
Application 18/735,514 is a continuation of application No. 17/607,278, granted, now 12,033,033, previously published as PCT/US2020/037222, filed on Jun. 11, 2020.
Claims priority of provisional application 62/860,098, filed on Jun. 11, 2019.
Prior Publication US 2024/0403684 A1, Dec. 5, 2024
Int. Cl. G06N 10/40 (2022.01); H10N 60/12 (2023.01); H10N 60/80 (2023.01)
CPC G06N 10/40 (2022.01) [H10N 60/12 (2023.02); H10N 60/805 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A quantum processor comprising a plurality of tiles, the plurality of tiles arranged in a first grid, each tile of the plurality of tiles comprising:
a shift register comprising at least one shift register stage communicatively coupled to a frequency-multiplexed resonant (FMR) readout;
one or more qubits of a plurality of qubits of the quantum processor;
one or more qubit readout devices, wherein the one or more qubit devices are communicatively coupled to the shift register, and each one of the one or more qubit readout devices is communicatively coupled to a respective one of the one or more qubits;
a plurality of digital-to-analog converter (DAC) buffer stages communicatively coupled to the shift register;
a plurality of shift-register-loadable DACs arranged in a second grid, wherein each one of the shift-register-loadable DACs is communicatively coupled to one of the plurality of DAC buffer stages; and
a plurality of control structures, wherein each control structure is operable to control a respective tile of the plurality of tiles, and a subset of the plurality of control structures share analog lines that are identically coupled to at least one of: respective pluralities of shift register stages and respective pluralities of shift-register-loadable DACs of correspondingly coupled tiles such that the subset of the plurality of control structures are operable to perform parallel input/output (I/O) operations among a subset of the plurality of tiles that comprises the correspondingly coupled tiles.