US 12,475,362 B2
Method for controlling neural network circuit
Koumei Tomida, Tokyo (JP); and Nikolay Nez, Tokyo (JP)
Assigned to MAXELL, LTD., Kyoto (JP)
Appl. No. 17/917,795
Filed by MAXELL, LTD., Kyoto (JP)
PCT Filed Apr. 12, 2021, PCT No. PCT/JP2021/015148
§ 371(c)(1), (2) Date Oct. 7, 2022,
PCT Pub. No. WO2021/210527, PCT Pub. Date Oct. 21, 2021.
Claims priority of application No. 2020-071933 (JP), filed on Apr. 13, 2020.
Prior Publication US 2023/0138667 A1, May 4, 2023
Int. Cl. G06N 3/063 (2023.01); G06F 9/52 (2006.01); G06N 3/0464 (2023.01)
CPC G06N 3/063 (2013.01) [G06F 9/526 (2013.01); G06N 3/0464 (2023.01)] 11 Claims
OG exemplary drawing
 
1. A method for controlling a neural network circuit comprising:
a first memory that stores input data;
a convolution operation circuit that performs a convolution operation on the input data stored in the first memory;
a second memory that stores convolution operation output data from the convolution operation circuit;
a quantization operation circuit that performs a quantization operation on the convolution operation output data stored in the second memory;
a second write semaphore that controls writing into the second memory by the convolution operation circuit;
a second read semaphore that controls reading from the second memory by the quantization operation circuit;
a third write semaphore that controls writing into the first memory by the quantization operation circuit;
a third read semaphore that controls reading from the first memory by the convolution operation circuit;
wherein the method for controlling the neural network circuit involves
making the convolution operation circuit implement a convolution operation based on the third read semaphore and the second write semaphore;
wherein the neural network circuit further comprising a DMA controller that transfers the input data to the first memory;
a first write semaphore that controls writing into the first memory by the DMA controller; and
a first read semaphore that controls reading from the first memory by the convolution operation circuit;
wherein the method for controlling the neural network circuit involves
making the convolution operation circuit implement the convolution operation based on the first read semaphore and the second write semaphore; and
wherein the neural network circuit is embeddable in an embedded device.