US 12,475,286 B1
System and method for comparing circuit design constraint sets
Jeannette Newman Sutherland, Cedar Park, TX (US); Amit Dhuria, Fremont, CA (US); Arvind Nembili Veeravalli, Bangalore (IN); Sarath Jayalath Kirihennedige, Fair Oaks, CA (US); and Saulius Kersulis, Pleasanton, CA (US)
Assigned to Cadence Design Systems, Inc., San Jose, CA (US)
Filed by Cadence Design Systems, Inc., San Jose, CA (US)
Filed on Jun. 15, 2022, as Appl. No. 17/841,056.
Int. Cl. G06F 30/3312 (2020.01); G06F 111/04 (2020.01); G06F 119/12 (2020.01)
CPC G06F 30/3312 (2020.01) [G06F 2111/04 (2020.01); G06F 2119/12 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A computer-implemented method for comparing constraint sets of a circuit design, comprising:
determining, using at least one processor, at least one arrival propagation time corresponding to at least one endpoint, the at least one endpoint associated with a first constraint set and a second constraint set of the circuit design;
creating, using the at least one processor, a first tag associated with the first constraint set and a second tag associated with the second constraint set;
determining, using the at least one processor, at least one of:
a non-equivalent path exception corresponding to the at least one endpoint and based at least in part on at least one of the arrival propagation time, the first tag, and the second tag; and
an equivalent path exception corresponding to the at least one endpoint and based at least in part on the arrival propagation time, the first tag, and the second tag, wherein determining at least one of a non-equivalent path and an equivalent path includes comparing all constraints of the first constraint set with all constraints of the second constraint set; and
indicating, using the at least one processor, at least one of the non-equivalent path exception and the equivalent path exception.