US 12,475,283 B2
Generating and display an animation of a predicted overlap shape in an IC design
Donald Oriordan, Sunnyvale, CA (US); Akira Fujimura, Saratoga, CA (US); and George Janac, Saratoga, CA (US)
Assigned to D2S, INC., San Jose, CA (US)
Filed by D2S, Inc., San Jose, CA (US)
Filed on Nov. 22, 2022, as Appl. No. 17/992,907.
Claims priority of provisional application 63/300,675, filed on Jan. 19, 2022.
Prior Publication US 2023/0229836 A1, Jul. 20, 2023
Int. Cl. G06F 30/31 (2020.01); G06F 30/392 (2020.01); G06F 30/398 (2020.01); G06N 3/08 (2023.01)
CPC G06F 30/31 (2020.01) [G06F 30/392 (2020.01); G06F 30/398 (2020.01); G06N 3/08 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of designing an integrated circuit (IC) with a plurality of circuit elements, the method comprising:
for a layout of an IC design that has a plurality of interconnect layers and a multi-layer interface (i) connecting at least two IC-design circuit elements on a set of at least two interconnect layers and (ii) comprising at least two components on the set of interconnect layers:
commencing an animation process to generate, for display on a display area of a user interface (UI), a first rendering of a first predicted minimum overlap shape for the multi-layer interface;
processing one or more inputs that are received through the UI with respect to the multi-layer interface; and
after a duration of time, displaying a second rendering of a second predicted minimum overlap shape for the multi-layer interface that is generated by the animation process, the first and second minimum overlap shapes being first and second shapes that are predicted to be produced after a manufacturing stage of a manufacturing process that is used to manufacture a semiconductor circuit from the design layout.