US 12,475,188 B2
Compute time point processor array for solving partial differential equations
Chirath Neranjena Thouppuarachchi, Redwood City, CA (US); and Ross Geoffrey Daly, San Francisco, CA (US)
Assigned to Vorticity Inc., Redwood City, CA (US)
Filed by Vorticity Inc., Redwood City, CA (US)
Filed on Jan. 14, 2022, as Appl. No. 17/576,795.
Claims priority of provisional application 63/137,921, filed on Jan. 15, 2021.
Prior Publication US 2022/0229880 A1, Jul. 21, 2022
Int. Cl. G06F 17/13 (2006.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 7/57 (2006.01)
CPC G06F 17/13 (2013.01) [G06F 9/3001 (2013.01); G06F 9/3851 (2013.01); G06F 7/57 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system, comprising:
a memory configured to store a plurality of nodes of a domain corresponding to a first time-step, the nodes associated with a partial differential equation having a discretized form;
an array of configurable point processors, each point processor comprising:
an arithmetic logic unit (ALU) configurable to perform one or more arithmetic operations on a node value received by the point processor; and
a register file configurable to store node value data received by the point processor, and to communicate with at least one neighboring point processor of the array;
a controller configured to process the plurality of nodes of the domain using the array of point processors by providing a respective node of the plurality of nodes to each point processor of the array of point processors, and an instruction stream for configuring a point processor of the array of point processors to at least a portion of the array of point processors;
wherein each point processor of the array of point processors processes its respective node to generate node data for a next time step of the domain by applying a plurality of instructions of the instruction stream to data of its respective node.