US 12,475,069 B2
Dynamic power gating using deterministic interconnect
Nikhil Sangani, Bangalore (IN); Mihir Mody, Bangalore (IN); Malav Shah, Bangalore (IN); Athavan Arasumani, Pondicherry (PY); and Shailesh Ghotgalkar, Bangalore (IN)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Oct. 31, 2023, as Appl. No. 18/498,581.
Claims priority of application No. 202341043216 (IN), filed on Jun. 28, 2023.
Prior Publication US 2025/0139031 A1, May 1, 2025
Int. Cl. G06F 13/20 (2006.01)
CPC G06F 13/20 (2013.01) [G06F 2213/40 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A microcontroller unit, comprising:
a group of processing devices;
a group of target resources;
interconnect circuitry that connects the group of processing devices to the group of target resources;
clock control circuitry coupled to the interconnect circuitry and configurable to:
receive inputs indicative of events in the interconnect circuitry;
select a clock enabling mode, of multiple clock enabling modes, for communication between a processing device of the group of processing devices and a target resource of the group of target resources;
predict an upcoming occurrence of a communication between the processing device and the target resource based on a subset of the inputs related to the selected clock enabling mode; and
prior to the occurrence of the communication, enable a clock associated with a path through the interconnect circuitry between the processing device and the target resource based on the prediction.