US 12,475,067 B2
Methods for performing multiple memory operations in response to a single command and memory devices and systems employing the same
Matthew A. Prather, Boise, ID (US); Frank F. Ross, Boise, ID (US); and Randall J. Rooney, Boise, ID (US)
Filed by Lodestar Licensing Group LLC, Evanston, IL (US)
Filed on Sep. 27, 2023, as Appl. No. 18/373,769.
Application 18/373,769 is a continuation of application No. 17/712,006, filed on Apr. 1, 2022, granted, now 11,775,459.
Application 17/712,006 is a continuation of application No. 17/074,281, filed on Oct. 19, 2020, granted, now 11,294,836, issued on Apr. 5, 2022.
Application 17/074,281 is a continuation of application No. 16/543,482, filed on Aug. 16, 2019, granted, now 10,810,145, issued on Oct. 20, 2020.
Application 17/074,281 is a continuation of application No. 16/432,413, filed on Jun. 5, 2019, granted, now 10,846,248, issued on Dec. 5, 2019.
Application 16/543,482 is a continuation of application No. 16/030,740, filed on Jul. 9, 2018, granted, now 10,552,087, issued on Dec. 5, 2019.
Application 16/432,413 is a continuation of application No. 16/030,746, filed on Jul. 9, 2018, granted, now 10,489,316, issued on Nov. 26, 2019.
Claims priority of provisional application 62/680,422, filed on Jun. 4, 2018.
Prior Publication US 2024/0126707 A1, Apr. 18, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 13/00 (2006.01); G06F 3/06 (2006.01); G06F 13/16 (2006.01); G06F 13/40 (2006.01); G11C 7/22 (2006.01); G11C 11/406 (2006.01)
CPC G06F 13/1689 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0625 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G06F 13/4086 (2013.01); G11C 7/22 (2013.01); G11C 11/406 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A memory system, comprising:
a plurality of memory portions; and
circuitry configured, in response to receiving a first command and a second command within a first duration, to:
perform a refresh operation at a first memory portion of the plurality of memory portions; and
perform a mode register read operation of a different kind than the refresh operation at the first memory portion.