US 12,475,065 B2
Flash arbitration in heterogeneous computing platforms
Adolfo S. Montero, Pflugerville, TX (US); Abeye Teshome, Austin, TX (US); and Alok Pant, Austin, TX (US)
Assigned to Dell Products, L.P., Round Rock, TX (US)
Filed by Dell Products, L.P., Round Rock, TX (US)
Filed on Aug. 2, 2023, as Appl. No. 18/363,967.
Prior Publication US 2025/0045218 A1, Feb. 6, 2025
Int. Cl. G06F 13/16 (2006.01)
CPC G06F 13/1673 (2013.01) [G06F 2213/0002 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An Information Handling System (IHS), comprising:
a heterogeneous computing platform comprising a plurality of devices, wherein each of the plurality of devices is associated with a respective buffer; and
a flash memory external to the heterogeneous computing platform and coupled to the plurality of devices via a Serial Peripheral Interface (SPI) controller, wherein the heterogeneous computing platform further comprises a flash arbitration circuit coupled between the SPI controller and the plurality of devices, and wherein the flash arbitration circuit is configured to arbitrate access to the flash memory among the plurality of devices;
wherein, to arbitrate access to the flash memory, the flash arbitration circuit is configured to interleave access cycles for each of the plurality of devices based, at least in part, upon a fill level of each respective buffer; and
wherein, in response to a first one of the plurality of devices having a buffer with a first current fill level and a second one of the plurality of devices having a buffer with a second current fill level, the flash arbitration circuit is configured to allocate a first flash memory access time slot to the first device proportional to the first current fill level and a second flash memory access time slot to the second device proportional to the second current fill level.