US 12,475,064 B2
Network on Chip processing system
Stefan Blixt, Bålsta (SE)
Assigned to Telesis Innovation AB, Bålsta (SE)
Appl. No. 18/259,235
Filed by TELESIS INNOVATION AB, Balsta (SE)
PCT Filed Dec. 20, 2021, PCT No. PCT/SE2021/051294
§ 371(c)(1), (2) Date Jun. 23, 2023,
PCT Pub. No. WO2022/139666, PCT Pub. Date Jun. 30, 2022.
Claims priority of provisional application 63/130,089, filed on Dec. 23, 2020.
Prior Publication US 2025/0307204 A1, Oct. 2, 2025
Int. Cl. G06F 9/22 (2006.01); G06F 15/173 (2006.01); G06F 15/78 (2006.01)
CPC G06F 15/7825 (2013.01) [G06F 15/17337 (2013.01)] 23 Claims
OG exemplary drawing
 
1. A Network on Chip, NoC, processing system configured to perform data processing, wherein said NoC processing system is configured for interconnection with a control processor connectable to said NoC processing system, said NoC processing system comprising:
a plurality of microcode-programmable Processing Elements, PEs, organized in multiple clusters, each cluster comprising a multitude of said programmable PEs, the functionality of each microcode-programmable Processing Element being defined by internal microcode in a microprogram memory associated with the Processing Element,
wherein said multiple clusters of programmable Processing Elements are arranged on a Network on Chip, NoC, said Network on Chip having a root and a plurality of peripheral nodes, wherein said multiple clusters of Processing Elements are arranged at peripheral nodes of the Network on Chip, and wherein said Network on Chip is connectable to said control processor at said root;
wherein each cluster further includes a Cluster Controller, CC, and an associated Cluster Memory, CM, shared by the multitude of programmable Processing Elements within the cluster;
wherein the Cluster Memory of each cluster is configured to store at least microcode received from an on-chip or off-chip data source under the control of said connectable control processor, and each Processing Element within a cluster is configured to request microcode from the associated Cluster Memory;
wherein the Cluster Controller of each cluster is configured to enable transfer of microcode from the associated Cluster Memory to at least a subset of the Processing Elements within the cluster in response to requests from the corresponding Processing Elements.