US 12,475,059 B2
Maintaining contiguity of virtual to physical address mappings to exploit contiguity-aware translation look-aside buffer hardware
Aravinda Prasad, Bangalore (IN); and Sreenivas Subramoney, Bangalore (IN)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on May 26, 2022, as Appl. No. 17/825,977.
Prior Publication US 2022/0283954 A1, Sep. 8, 2022
Int. Cl. G06F 12/1036 (2016.01)
CPC G06F 12/1036 (2013.01) [G06F 2212/2542 (2013.01); G06F 2212/68 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A non-transitory machine-readable medium storing instructions, which when executed by a processing resource of a monitor node of a shared memory system cause the shared memory system to:
determine whether migration of a set of one or more pages within a first continuous region of physical memory addresses of a physical address space from a source tier of memory to a target tier of memory, would break contiguity of a mapping maintained by a contiguity-aware translation lookaside buffer (TLB) between pages of the first contiguous region and a second contiguous region of a virtual memory area (VMA) corresponding to the first contiguous region; and
responsive to an affirmative determination, minimize a number of discontinuities within the mapping resulting from the migration by (i) increasing the set by adding up to N pages of the first contiguous region to the set, or (ii) decreasing the set by removing up to M pages of the set from the set.