US 12,475,057 B2
Pipelined out of order page miss handler
Christopher D. Bryant, Austin, TX (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Oct. 25, 2023, as Appl. No. 18/494,164.
Application 18/494,164 is a continuation of application No. 16/914,324, filed on Jun. 27, 2020, granted, now 11,822,486.
Prior Publication US 2024/0054077 A1, Feb. 15, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/1009 (2016.01)
CPC G06F 12/1009 (2013.01) [G06F 2212/651 (2013.01)] 20 Claims
OG exemplary drawing
 
8. A method comprising:
translating virtual addresses to physical addresses with a translation lookaside buffer of a system; and
performing, by a single instance of hardware comprising a plurality of pipelined page walk stages of the system, a plurality of contemporaneous page walks for corresponding misses in the translation lookaside buffer without replication of the hardware a number of times equal to the plurality of contemporaneous page walks.