US 12,475,055 B2
Processor support for using cache way-locking to simultaneously record plural execution contexts into independent execution traces
Jordi Mola, Bellevue, WA (US)
Assigned to Microsoft Technology Licensing, LLC, Redmond, WA (US)
Appl. No. 18/553,818
Filed by Microsoft Technology Licensing, LLC, Redmond, WA (US)
PCT Filed Apr. 18, 2022, PCT No. PCT/US2022/071780
§ 371(c)(1), (2) Date Oct. 3, 2023,
PCT Pub. No. WO2022/226485, PCT Pub. Date Oct. 27, 2022.
Claims priority of application No. 500061 (LU), filed on Apr. 20, 2021.
Prior Publication US 2024/0193092 A1, Jun. 13, 2024
Int. Cl. G06F 12/08 (2016.01); G06F 11/30 (2006.01); G06F 12/0891 (2016.01); G06F 12/0895 (2016.01)
CPC G06F 12/0895 (2013.01) [G06F 11/3037 (2013.01); G06F 12/0891 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A processor comprising:
a processing unit;
a memory cache; and
control logic that configures the processor to record plural execution contexts that execute at the processing unit into independent execution traces by:
partitioning the memory cache into a plurality of memory cache subsets that include: (i) a first memory cache subset comprising a first set of memory cache ways that are locked to a first execution context whose execution at the processing unit is being recorded into a first trace buffer, and (ii) a second memory cache subset comprising a second set of memory cache ways that are locked to a second execution context whose execution at the processing unit is being recorded into a second trace buffer;
detecting a first memory operation by the first execution context, the first memory operation targeting a memory address associated with the second memory cache subset; and
in response to detecting the first memory operation, performing at least one of:
(i) when the first memory operation causes a first influx into the second memory cache subset, initiating logging of the first influx to the second trace buffer;
(ii) when the first memory operation is a first read from the second memory cache subset, initiating logging of the first read to the first trace buffer; or
(iii) when the first memory operation is a first write to the second memory cache subset, performing one of (a) initiating logging of the first write to the second trace buffer, or (b) evicting a first cache line that is a target of the first write.