US 12,475,052 B2
Memory systems and methods for operating memory systems
Daehoon Kim, Gimpo-si (KR); Hyungwon Park, Daegu (KR); Jin Jung, Suwon-si (KR); Minho Kim, Daegu (KR); Jin In So, Suwon-si (KR); Jong-Geon Lee, Suwon-si (KR); Hwanjun Lee, Daegu (KR); Minwoo Jang, Daegu (KR); and Yeaji Jung, Busan (KR)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (KR); and Daegu Gyeongbuk Institute of Science and Technology, Daegu (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Mar. 14, 2024, as Appl. No. 18/604,783.
Claims priority of application No. 10-2023-0116307 (KR), filed on Sep. 1, 2023.
Prior Publication US 2025/0077433 A1, Mar. 6, 2025
Int. Cl. G06F 12/0862 (2016.01)
CPC G06F 12/0862 (2013.01) 20 Claims
OG exemplary drawing
 
1. A memory system comprising:
a first memory;
a second memory having an operating speed different from that of the first memory;
a storage unit configured to store an instruction;
a prefetcher configured to update prefetcher data in response to occurrence of cache hits; and
a processor configured to execute the instruction stored in the storage unit,
wherein, when the instruction is executed by the processor, the processor is configured to:
generate prefetcher friendly data by filtering the prefetcher data,
set a prefetcher friendly bit in a first pointer area corresponding to the first memory and a second pointer area corresponding to the second memory based on the prefetcher friendly data, and
migrate first data in the first pointer area to the second pointer area or maintain the first data in the first pointer area, in consideration of a reference bit and the prefetcher friendly bit of the first and second pointer areas, and
migrate second data in the second pointer area to the first pointer area or maintain the second data in the second pointer area, in consideration of the reference bit and the prefetcher friendly bit of the first and second pointer areas.