US 12,475,050 B2
Cache-coherent interconnect based near-data-processing accelerator
Wenqin Huangfu, San Jose, CA (US); Krishna T. Malladi, San Jose, CA (US); and Andrew Chang, Los Altos, CA (US)
Assigned to SAMSUNG ELECTRONICS CO., LTD., (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jun. 7, 2022, as Appl. No. 17/834,896.
Claims priority of provisional application 63/316,399, filed on Mar. 3, 2022.
Prior Publication US 2023/0281128 A1, Sep. 7, 2023
Int. Cl. G06F 12/08 (2016.01); G06F 9/52 (2006.01); G06F 12/0817 (2016.01); G06F 12/0831 (2016.01)
CPC G06F 12/0828 (2013.01) [G06F 9/52 (2013.01); G06F 12/0831 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A memory system, comprising:
a first cache-coherent interconnect memory module;
a second cache-coherent interconnect memory module;
a cache-coherent interconnect switch connecting the first cache-coherent interconnect memory module, the second cache-coherent interconnect memory module, and a processor; and
a processing element to process a data stored on at least one of the first cache-coherent interconnect memory module and the second cache-coherent interconnect memory module to generate a second data,
wherein the processing element is included in the first cache-coherent interconnect memory module.