US 12,475,009 B1
Continuing to test a hardware component after occurrence of a checkstop
Divya Kumudprakash Joshi, Hobli (IN); Edward J. Kaminski, Jr., Wynnewood, PA (US); Kyle Davis, Pflugerville, TX (US); and Shaun Thomas Uldrikis, Hyde Park, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Sep. 24, 2024, as Appl. No. 18/894,242.
Int. Cl. G06F 11/00 (2006.01); G06F 11/26 (2006.01)
CPC G06F 11/261 (2013.01) 20 Claims
OG exemplary drawing
 
1. A computer-implemented method for testing hardware in an environment involving a checkstop, the method comprising:
injecting errors into a model of a design under test comprising a first hardware component and a second hardware component at various states causing an occurrence of a checkstop in said first hardware component, wherein said first hardware component is interfaced with said second hardware
performing a simulation of said model of said design under test with said injected errors for a number of cycles after said checkstop based on a quiesce time where said injected errors are suppressed;
executing a post-processing script to test said model of said design under test which ignores errors of said first hardware component that were identified after said checkstop in said simulation of said model of said design under test;
analyzing a non-ignored error from said execution of said post-processing script; and
outputting an indication that said second hardware component failed said test after said occurrence of said checkstop in response to said analyzed error causing said model of said design under test to fail said test.