US 12,474,865 B2
Write booster buffer and hibernate
Luca Porzio, Casalnuovo (IT); and Deping He, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 7, 2024, as Appl. No. 18/598,985.
Application 18/598,985 is a continuation of application No. 17/645,265, filed on Dec. 20, 2021, granted, now 11,934,692.
Prior Publication US 2024/0289050 A1, Aug. 29, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0656 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0634 (2013.01); G06F 3/0653 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory system, comprising:
one or more memory devices; and
processing circuitry coupled with the one or more memory devices and configured to cause the memory system to:
initiate, at the memory system, a first operation to enter a first power mode having a lower power consumption than a second power mode;
determine whether a total bytes written to the memory system satisfies a threshold based at least in part on initiating the first operation; and
enter the first power mode based at least in part on determining that the total bytes written to the memory system satisfies the threshold and further based at least in part on a quantity of data stored in a buffer of single-level cells.