US 12,474,857 B2
Memory system
Akifumi Fukuda, Yokohama Kanagawa (JP); and Kenta Yasufuku, Yokohama Kanagawa (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Mar. 3, 2023, as Appl. No. 18/178,422.
Claims priority of application No. 2022-099789 (JP), filed on Jun. 21, 2022.
Prior Publication US 2023/0409229 A1, Dec. 21, 2023
Int. Cl. G06F 3/00 (2006.01); G06F 3/06 (2006.01); G06F 12/00 (2006.01)
CPC G06F 3/0653 (2013.01) [G06F 3/0656 (2013.01); G06F 3/0658 (2013.01); G06F 3/0679 (2013.01); G06F 3/0604 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A memory system comprising:
a non-volatile memory; and
a controller including a memory having a lower access latency than the non-volatile memory, the controller configured to:
temporarily store, in the memory, data to be written into the non-volatile memory and data read from the non-volatile memory;
track logical addresses of data stored in the non-volatile memory that were subject to a first limited number of recent wear leveling processes, in a ring buffer configured in the memory of the controller;
perform a current wear leveling process on first data stored in the non-volatile memory, and determine whether an logical address of the first data subject to the current wear leveling process is included in the tracked logical addresses and whether the first data is stored in the memory; and
upon determining that the logical address of the first data is included in the tracked logical addresses and that the first data is stored in the memory, perform a pinning process to disable overwrite of the first data stored in the memory.