| CPC G06F 3/0613 (2013.01) [G06F 3/0631 (2013.01); G06F 3/0673 (2013.01)] | 18 Claims |

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1. A memory, comprising:
a bank, the bank comprises two planes, wherein each of the two planes comprises a plurality of memory resources and a plurality of redundant replacement resources; and
a bad memory resource of one of the two planes is capable of being replaced by a redundant replacement resource of an other of the two planes for performing a normal Read/Write operation,
at least one of the plurality of memory resources comprises a column memory resource, at least one of the plurality of redundant replacement resources comprises a column redundant replacement resource;
the bank comprises a column decoding circuit;
in response to a mode signal being a first logic level, the column decoding circuit is only capable of enabling the column redundant replacement resource in one of the two planes to replace a bad column memory resource in a same plane;
in response to the mode signal being a second logic level, the column decoding circuit is capable of enabling the column redundant replacement resources in the one of the two planes to replace the bad column memory resource in an other of the two planes; and
the first logic level is different from the second logic level.
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