| CPC G06F 3/0418 (2013.01) [G06F 3/0412 (2013.01); G06F 3/04164 (2019.05); G06F 3/04166 (2019.05); G09G 3/2096 (2013.01); G06F 3/0446 (2019.05); G09G 3/32 (2013.01); G09G 3/3225 (2013.01); G09G 3/3648 (2013.01); G09G 2310/0297 (2013.01); G09G 2330/06 (2013.01); G09G 2354/00 (2013.01)] | 20 Claims |

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1. A voltage and phase compensation circuit comprising:
a first inverting adder configured to add and invert a plurality of panel signals to output a first inverted signal;
a second inverting adder configured to add and invert feedback signals obtained from delayed panel signals and the first inverted signal to output a second inverted signal; and
a coupler configured to combine the first inverted signal and the second inverted signal.
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