US 12,474,763 B2
Processor power management utilizing dedicated DMA engines
Ling-Ling Wang, Santa Clara, CA (US); Yuan Du, Shanghai (CN); ZengRong Huang, Shanghai (CN); HaiKun Dong, Beijing (CN); LingFei Shi, Shanghai (CN); Wei Shao, Beijing (CN); XiaoJing Ma, Shanghai (CN); Qian Zong, Shanghai (CN); and Shenyuan Chen, Shanghai (CN)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Sep. 30, 2021, as Appl. No. 17/490,003.
Prior Publication US 2023/0098742 A1, Mar. 30, 2023
Int. Cl. G06F 1/00 (2006.01); G06F 1/3296 (2019.01); G06F 9/48 (2006.01); G06F 13/28 (2006.01)
CPC G06F 1/3296 (2013.01) [G06F 9/4893 (2013.01); G06F 13/28 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A processor comprising:
a first direct memory access (DMA) engine comprising circuitry configured to transfer data between an external memory and a first partition of the processor that provides a first functionality, wherein the first partition is in a first power domain;
a second direct memory access (DMA) engine comprising circuitry configured to transfer data between the external memory and a second partition of the processor, wherein the second partition is configured to provide a second functionality different from the first functionality, wherein the second partition is in a second power domain that is independent of the first power domain; and
control circuitry configured to receive a task and, based on a type of the task, assign the task to either the first partition or the second partition for execution, wherein the first and second partitions operate independently and concurrently under respective power domains and respective DMA engines.