| CPC G06F 1/04 (2013.01) | 20 Claims |
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1. A deserializer comprising:
a shift register circuit configured to output N output data by shifting input data based on a first clock signal, where ‘N’ is a natural number;
a clock divider configured to output N second clock signals N-divided from the first clock signal and having N phases different from each other, and to output one or more third clock signals divided to have a frequency less than that of the second clock signals;
a clock selecting circuit configured to output a selected clock signal having an edge corresponding to a second time after N number of clock cycles of the first clock signal have elapsed from a first time at which a valid period is detected in a selection signal for selecting the input data, based on the N second clock signals and the one or more third clock signals; and
a data align circuit configured to parallelize the N output data based on the selected clock signal.
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