US 12,474,647 B2
Generating an alignment signal based on local alignment mark distortions
Zahrasadat Dastouri, Norwalk, CT (US); Igor Matheus Petronella Aarts, Port Chester, NY (US); Simon Gijsbert Josephus Mathijssen, Rosmalen (NL); and Peter David Engblom, Hillsboro, OR (US)
Assigned to ASML NETHERLANDS B.V., Veldhoven (NL); and ASML HOLDING N.V., Veldhoven (NL)
Appl. No. 17/922,922
Filed by ASML HOLDING N.V., Veldhoven (NL); and ASML NETHERLANDS B.V., Veldhoven (NL)
PCT Filed Apr. 22, 2021, PCT No. PCT/EP2021/060595
§ 371(c)(1), (2) Date Nov. 2, 2022,
PCT Pub. No. WO2021/233642, PCT Pub. Date Nov. 25, 2021.
Claims priority of provisional application 63/026,893, filed on May 19, 2020.
Prior Publication US 2023/0176494 A1, Jun. 8, 2023
Int. Cl. G03F 9/00 (2006.01); G03F 7/00 (2006.01)
CPC G03F 9/7088 (2013.01) [G03F 7/70633 (2013.01); G03F 9/7049 (2013.01); G03F 9/7092 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for adjusting a semiconductor device manufacturing parameter, the method comprising:
detecting one or more local dimensional distortions of an alignment mark using a first measurement to detect local dimensional distortions; and
generating, based on the alignment mark, an alignment signal using a second different measurement to determine alignment, at least part of the alignment signal representing a part of the alignment mark being weighted based on the one or more local dimensional distortions of the alignment mark differently than at least part of the alignment signal representing a different part of the alignment mark, the alignment signal configured to be used to adjust the semiconductor device manufacturing parameter.