US 12,474,519 B2
Photonics chip patterning with multiple photoresist layers
Brittany Hedrick, Lagrangeville, NY (US); Ian Melville, Highland, NY (US); Michael David Webster, Poughkeepsie, NY (US); Harry Cox, Rifton, NY (US); Jorge Lubguban, Danbury, CT (US); and Sarah Knickerbocker, East Fishkill, NY (US)
Assigned to GlobalFoundries U.S. Inc., Malta, NY (US)
Filed by GlobalFoundries U.S. Inc., Malta, NY (US)
Filed on May 26, 2023, as Appl. No. 18/202,337.
Prior Publication US 2024/0393523 A1, Nov. 28, 2024
Int. Cl. G02B 6/12 (2006.01); F21V 8/00 (2006.01); G02B 6/122 (2006.01)
CPC G02B 6/0065 (2013.01) [G02B 6/1225 (2013.01); G02B 6/1228 (2013.01); G02B 6/12011 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of forming a structure for a photonics chip, the method comprising:
forming a first opening in a semiconductor substrate of the photonics chip;
forming a first photoresist layer that bridges the first opening on a first portion of the photonics chip, wherein the first photoresist layer comprises a dry-film photoresist;
forming a second photoresist layer on a second portion of the photonics chip, wherein the second photoresist layer comprises a liquid-based photoresist;
patterning the second photoresist layer to form a second opening that extends to an area on the photonics chip;
forming a first electrical interconnect on the area of the photonics chip, wherein the first electrical interconnect is a redistribution layer;
removing the first photoresist layer and the second photoresist layer;
forming a third photoresist layer that bridges the first opening on the first portion of the photonics chip;
forming a fourth photoresist layer on the second portion of the photonics chip;
patterning the fourth photoresist layer to form a third opening that exposes the redistribution layer; and
forming a second electrical interconnect on the redistribution layer.