US 12,474,401 B2
Systems and methods for isolating faults in die-to-die interconnects
Terrence Huat Hin Tan, Bayan Lepas (MY); Charles Walter Boecker, Ames, IA (US); Ravi Shivnaraine, Pickering (CA); Edwin Magtoto Gozun, Folsom, CA (US); and Sokratis Vamvakos, Sunnyvale, CA (US)
Assigned to Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed by Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed on Sep. 11, 2023, as Appl. No. 18/464,529.
Prior Publication US 2025/0085341 A1, Mar. 13, 2025
Int. Cl. G01R 31/28 (2006.01); G01R 31/66 (2020.01)
CPC G01R 31/2896 (2013.01) [G01R 31/2884 (2013.01); G01R 31/66 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a first die coupled to a second die via a die-to-die interconnect;
a first transmission path, along the die-to-die interconnect, from a transmitter associated with the first die to an asynchronous buffer associated with the second die;
a second transmission path from voltage reference circuitry associated with the second die to the asynchronous buffer associated with the second die, wherein the voltage reference circuitry is configured to selectively output a first voltage or a second voltage, different from the first voltage; and
control circuitry configured to simultaneously enable both the first transmission path and the second transmission path to allow the asynchronous buffer to receive inputs from both the transmitter associated with the first die and the voltage reference circuitry associated with the second die, wherein the inputs received by the asynchronous buffer are indicative of: (1) no failure in the die-to-die interconnect, (2) an open failure in the die-to-die interconnect, or (3) a short failure in the die-to-die interconnect.