US 12,474,399 B2
Analog test devices for integrated circuits with multiple power domains
Prashant Goyal, Noida (IN); and Vigyan Jain, Rewari (IN)
Assigned to NXP B.V., Eindhoven (NL)
Filed by NXP B.V., Eindhoven (NL)
Filed on May 12, 2023, as Appl. No. 18/316,554.
Claims priority of application No. 202341028358 (IN), filed on Apr. 19, 2023.
Prior Publication US 2024/0353478 A1, Oct. 24, 2024
Int. Cl. G01R 31/28 (2006.01)
CPC G01R 31/2884 (2013.01) [G01R 31/2896 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
an analog test bus;
a plurality of analog circuits including a first analog circuit, each of the plurality of analog circuits associated with a corresponding one of a plurality of power domains;
a first plurality of transmission gates coupled between the first analog circuit and the analog test bus; and
a first protection device coupled between the first plurality of transmission gates and a ground reference.