US 12,144,271 B2
Back end of line embedded RRAM structure with low forming voltage
Oleg Gluschenkov, Tannersville, NY (US); Alexander Reznicek, Troy, NY (US); Youngseok Kim, Upper Saddle River, NJ (US); Injo Ok, Loudonville, NY (US); and Soon-Cheon Seo, Glenmont, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on Aug. 11, 2021, as Appl. No. 17/444,841.
Prior Publication US 2023/0051052 A1, Feb. 16, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H10N 70/00 (2023.01); H10B 63/00 (2023.01); H10N 70/20 (2023.01)
CPC H10N 70/8833 (2023.02) [H10B 63/30 (2023.02); H10B 63/80 (2023.02); H10N 70/023 (2023.02); H10N 70/063 (2023.02); H10N 70/066 (2023.02); H10N 70/235 (2023.02); H10N 70/841 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure comprising:
a resistive random access memory device embedded between an upper metal interconnect and a lower metal interconnect in a backend structure of a chip, the resistive random access memory includes a first electrode and a second electrode separated by a dielectric film, wherein a portion of the dielectric film directly above the first electrode is crystalline;
a stud below and in electrical contact with the first electrode and the lower metal interconnect; and
a dielectric layer between the upper metal interconnect and the lower metal interconnect, the dielectric layer separates the upper metal interconnect from the lower metal interconnect.