US 12,144,268 B2
Semiconductor structure and method of manufacture
Kerem Akarvardar, Palo Alto, CA (US); Yu Chao Lin, Hsinchu (TW); Wei-Sheng Yun, Taipei (TW); Shao-Ming Yu, Zhubei (TW); Tzu-Chiang Chen, Hsinchu (TW); and Tung Ying Lee, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company Limited, Hsin-Chu (TW)
Filed by Taiwan Semiconductor Manufacturing Company Limited, Hsin-Chu (TW)
Filed on Feb. 15, 2022, as Appl. No. 17/671,731.
Prior Publication US 2023/0263081 A1, Aug. 17, 2023
Int. Cl. H10N 70/00 (2023.01); H10N 70/20 (2023.01)
CPC H10N 70/8418 (2023.02) [H10N 70/066 (2023.02); H10N 70/231 (2023.02); H10N 70/826 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a first dielectric layer;
an electrode in the first dielectric layer;
a second dielectric layer in the electrode; and
a phase change material over the first dielectric layer, the electrode, and the second dielectric layer, wherein:
an uppermost surface of the electrode is at least one of:
above an uppermost surface of the first dielectric layer,
above an uppermost surface of the second dielectric layer, or
above a lowermost surface of the phase change material.