US 12,143,828 B2
Sidelink synchronization signal block designs for shared spectrum
Chih-Hao Liu, San Diego, CA (US); Jing Sun, San Diego, CA (US); Yisheng Xue, San Diego, CA (US); and Xiaoxia Zhang, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Apr. 27, 2022, as Appl. No. 17/730,969.
Prior Publication US 2023/0354047 A1, Nov. 2, 2023
Int. Cl. H04W 16/00 (2009.01); H04L 1/00 (2006.01); H04L 5/00 (2006.01); H04W 16/14 (2009.01); H04W 56/00 (2009.01); H04W 72/0453 (2023.01); H04W 72/20 (2023.01)
CPC H04W 16/14 (2013.01) [H04L 1/0067 (2013.01); H04L 5/0051 (2013.01); H04W 56/001 (2013.01); H04W 72/0453 (2013.01); H04W 72/20 (2023.01)] 30 Claims
OG exemplary drawing
 
1. An apparatus for wireless communication at a first user equipment (UE), comprising:
a processor;
memory coupled with the processor; and
instructions stored in the memory and executable by the processor to cause the apparatus to:
perform a channel access procedure to gain access to a bandwidth part in a shared spectrum for sidelink communications with a second UE; and
transmit a signal to the second UE using one or more sub-bands of the bandwidth part, the signal comprising one or more sidelink synchronization signal blocks multiplexed with frequency resources associated with a physical sidelink shared channel, wherein the one or more sidelink synchronization signal blocks are transmitted using a set of symbol periods of a transmission time interval that are preceded by at least four initial symbols periods of the transmission time interval.