| CPC H04N 5/04 (2013.01) [G06T 1/20 (2013.01); H04N 19/44 (2014.11)] | 18 Claims |

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1. A signal processing device comprising:
a decoder configured to decode a first video data from a first video source and a second video data from a second video source, and to output the decoded first video data and second video data;
an image quality processor, in response to a common frame rate set based on a first frame rate of the first video data and a second frame rate of the second video data, configured to output the first video data based on the common frame rate;
a graphic processor configured to output the second video data based on the common frame rate;
a first image output interface configured to output the first video data to the image quality processor based on the common frame rate; and
a second image output interface configured to output the second video data to the graphic processor based on the common frame rate.
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