US 12,143,742 B2
Solid-state imaging element
Tomonori Yamashita, Kanagawa (JP)
Assigned to Sony Semiconductor Solutions Corporation, Kanagawa (JP)
Appl. No. 17/926,789
Filed by Sony Semiconductor Solutions Corporation, Kanagawa (JP)
PCT Filed May 11, 2021, PCT No. PCT/JP2021/017808
§ 371(c)(1), (2) Date Nov. 21, 2022,
PCT Pub. No. WO2021/251041, PCT Pub. Date Dec. 16, 2021.
Claims priority of application No. 2020-099445 (JP), filed on Jun. 8, 2020.
Prior Publication US 2023/0247324 A1, Aug. 3, 2023
Int. Cl. H04N 25/77 (2023.01); H04N 25/51 (2023.01); H04N 25/53 (2023.01); H04N 25/57 (2023.01)
CPC H04N 25/77 (2023.01) [H04N 25/51 (2023.01); H04N 25/53 (2023.01); H04N 25/57 (2023.01)] 15 Claims
OG exemplary drawing
 
1. A solid-state imaging element comprising:
a pixel unit including a plurality of pixels;
a pixel signal line that transmits a pixel signal of a corresponding pixel;
a reference signal line that transmits a reference signal to be compared with the pixel signal;
a first comparator that outputs a first output signal according to the pixel signal on a basis of a voltage difference between the pixel signal and the reference signal;
a second comparator that outputs a second output signal according to the pixel signal on a basis of the voltage difference between the pixel signal and the reference signal;
a first capacitor unit provided between the pixel signal line or the reference signal line and the first comparator and set to a first gain; and
a second capacitor unit provided between the pixel signal line or the reference signal line and the second comparator and set to a second gain, wherein
the first capacitor unit includes a first input capacitive element provided between the reference signal line and the first comparator, and a second input capacitive element provided between the pixel signal line and the first comparator,
the second capacitor unit includes a third input capacitive element provided between the reference signal line and the second comparator, and a fourth input capacitive element provided between the pixel signal line and the second comparator,
one end of each of the first and third input capacitive elements is commonly connected to the reference signal line,
one end of each of the second and fourth input capacitive elements is commonly connected to the pixel signal line,
the first comparator includes a first transistor having a gate commonly connected to other ends of the first and second input capacitive elements, and
the second comparator includes a second transistor having a gate commonly connected to other ends of the third and fourth input capacitive elements.