US 12,143,736 B2
Method, apparatus and system providing a storage gate pixel with high dynamic range
Parker Altice, Meridian, ID (US)
Filed by Lodestar Licensing Group LLC, Evanston, IL (US)
Filed on Jul. 6, 2022, as Appl. No. 17/858,894.
Application 17/858,894 is a continuation of application No. 17/322,480, filed on May 17, 2021, granted, now 11,582,411.
Application 17/322,480 is a continuation of application No. 16/715,662, filed on Dec. 16, 2019, granted, now 11,044,426, issued on Jun. 22, 2021.
Application 16/715,662 is a continuation of application No. 15/861,442, filed on Jan. 3, 2018, granted, now 10,523,881, issued on Dec. 31, 2019.
Application 15/861,442 is a continuation of application No. 15/231,287, filed on Aug. 8, 2016, granted, now 9,900,528, issued on Feb. 20, 2018.
Application 15/231,287 is a continuation of application No. 14/089,225, filed on Nov. 25, 2013, granted, now 9,412,779, issued on Aug. 9, 2016.
Application 14/089,225 is a continuation of application No. 13/216,664, filed on Aug. 24, 2011, granted, now 8,599,293, issued on Dec. 3, 2013.
Application 13/216,664 is a continuation of application No. 11/511,310, filed on Aug. 29, 2006, granted, now 8,026,966, issued on Sep. 27, 2011.
Prior Publication US 2023/0025262 A1, Jan. 26, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H04N 25/59 (2023.01); H01L 27/146 (2006.01); H04N 25/571 (2023.01); H04N 25/589 (2023.01); H04N 25/621 (2023.01); H04N 25/75 (2023.01); H04N 25/76 (2023.01); H04N 25/771 (2023.01)
CPC H04N 25/59 (2023.01) [H01L 27/14643 (2013.01); H01L 27/14656 (2013.01); H04N 25/575 (2023.01); H04N 25/589 (2023.01); H04N 25/622 (2023.01); H04N 25/75 (2023.01); H04N 25/76 (2023.01); H04N 25/771 (2023.01)] 30 Claims
OG exemplary drawing
 
1. A pixel circuit, comprising:
a floating diffusion region;
a first photosensor coupled to the floating diffusion region via a first series of transistors;
a first storage region coupled to the first photosensor, the first storage region positioned between a first transistor and a second transistor of the first series of transistors;
a third transistor coupled to the first photosensor and separate from the first series of transistors, wherein the third transistor is configured such that the first photosensor is reset at least when the third transistor is activated while the first transistor is off;
a second photosensor coupled to the floating diffusion region via a second series of transistors different from the first series of transistors; and
a second storage region coupled to the second photosensor, the second storage region positioned between a fourth transistor and a fifth transistor of the second series of transistors, wherein the pixel circuit is configured to pulse a first signal applied to a gate of the third transistor such that (a) the third transistor is activated and the first photosensor is reset and (b) the pulse of the first signal ends before a second signal applied to a gate of the first transistor is asserted.