CPC H04N 19/70 (2014.11) [H04N 19/463 (2014.11)] | 5 Claims |
1. An encoder comprising:
memory; and
circuitry coupled to the memory,
wherein in operation, the circuitry:
stores first information indicating a total number of temporal sub-layers into either a buffering period supplemental enhancement information (SEI) message or a picture timing SEI message; and
generates a bitstream including the buffering period SEI message and the picture timing SEI message,
wherein the buffering period SEI message includes a first loop structure of the total number of the temporal sub-layers indicated by the first information, and each of first loops includes an initial delay of a timing to extract data from a coded picture buffer (CPB),
wherein the picture timing SEI message includes a second loop structure of the total number of the temporal sub-layers indicated by the first information, and each of second loops includes a parameter related to the timing to extract data from the CPB,
wherein the buffering period SEI further includes second information indicating a total number of initial delays of the timing to extract data from the CPB, and
wherein a sequence parameter set includes third information having a value equal to the second information, the third information indicating a total number of schedules.
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