| CPC H04N 19/44 (2014.11) [H04N 19/13 (2014.11); H04N 19/423 (2014.11)] | 19 Claims |

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1. A context-based adaptive binary arithmetic coding (CABAC) decoder comprising:
a bin decode circuit, arranged to at least support decoding of multiple bins in one cycle, wherein the multiple bins comprise a first bin and a second bin, and the bin decode circuit generates a bin value of the first bin according to a first set of multiple contexts, a first range and a first offset, and generates one bin value of the second bin according to a second set of multiple contexts, a second range and a second offset, where each of the second range and the second offset depends on decoding of the first bin; and
a context update circuit, arranged to update the first set of multiple contexts in response to the bin value of the first bin, to generate a first set of multiple updated contexts; and further arranged to update the second set of multiple contexts in response to said one bin value of the second bin, to generate a second set of multiple updated contexts, wherein the context update circuit comprises:
a context update core circuit, arranged to:
generate the first set of multiple updated contexts according to the first set of multiple contexts, the bin value of the first bin, and a first set of multiple adaptation rates; and
generate the second set of multiple updated contexts according to the second set of multiple contexts, said one bin value of the second bin, and a second set of multiple adaptation rates;
a first multiplexer circuit, having a first input port arranged to receive the first set of updated multiple contexts, a second input port arranged to receive a third set of multiple contexts, and a first output port arranged to output the second set of multiple contexts to the context update core circuit, wherein the first multiplexer circuit is arranged to couple the first output port to one of the first input port and the second input port; and
a second multiplexer circuit, having a third input port arranged to receive the first set of multiple adaptation rates, a fourth input port arranged to receive a third set of multiple adaptation rates, and a second output port arranged to output the second set of multiple adaptation rates to the context update core circuit, wherein the second multiplexer circuit is arranged to couple the second output port to one of the third input port and the fourth input port.
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