US 12,143,608 B2
Encoder, decoder, encoding method, and decoding method
Virginie Drugeon, Darmstadt (DE); Kiyofumi Abe, Osaka (JP); Takahiro Nishi, Nara (JP); and Tadamasa Toma, Osaka (JP)
Assigned to PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA, Torrance, CA (US)
Filed by Panasonic Intellectual Property Corporation of America, Torrance, CA (US)
Filed on Jul. 27, 2022, as Appl. No. 17/874,731.
Application 17/874,731 is a continuation of application No. PCT/JP2021/012092, filed on Mar. 23, 2021.
Claims priority of provisional application 62/994,484, filed on Mar. 25, 2020.
Prior Publication US 2022/0368929 A1, Nov. 17, 2022
Int. Cl. H04N 19/423 (2014.01); H04N 19/31 (2014.01); H04N 19/70 (2014.01)
CPC H04N 19/423 (2014.11) [H04N 19/31 (2014.11); H04N 19/70 (2014.11)] 5 Claims
OG exemplary drawing
 
1. An encoder comprising:
circuitry; and
memory coupled to the circuitry, wherein
in operation, the circuitry:
given id indicating a lower temporal sublayer other than a highest temporal sublayer in temporal sublayers, subtracts a decoded picture buffer (DPB) output delta [id] from a DPB output delay to calculate a DPB output time [id] for a picture in the lower temporal sublayer, the DPB output delta [id] being provided for each of the temporal sublayers, the DPB output delay being shared between the temporal sublayers;
given maxid indicating the highest temporal sublayer, calculates the DPB output delta [id] by subtracting a coded picture buffer (CPB) removal delay [maxid] and an offset [id] from a CPB removal delay [id]; and
stores the offset [id] in a bitstream.