US 12,143,501 B2
ISA support for programming hardware over untrusted links
Siddhartha Chhabra, Portland, OR (US); Manjula Peddireddy, Santa Clara, CA (US); and Hormuzd Khosravi, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 26, 2020, as Appl. No. 17/134,352.
Prior Publication US 2022/0209959 A1, Jun. 30, 2022
Int. Cl. H04L 9/08 (2006.01); G06F 12/14 (2006.01); G06F 13/16 (2006.01); G06F 21/64 (2013.01); G06F 21/78 (2013.01); H04L 9/32 (2006.01); H04L 9/40 (2022.01); G06F 21/72 (2013.01); G06F 21/79 (2013.01)
CPC H04L 9/3242 (2013.01) [G06F 12/1408 (2013.01); G06F 13/1668 (2013.01); G06F 21/64 (2013.01); G06F 21/78 (2013.01); H04L 9/0819 (2013.01); H04L 9/0894 (2013.01); H04L 63/0428 (2013.01); H04L 63/123 (2013.01); G06F 21/72 (2013.01); G06F 21/79 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a far memory to be utilized as volatile memory; and
a far memory controller to receive a request from a near memory for a processor, the far memory controller to:
determine a type of request for the received request, and
for a read request to at least determine if a fast zero memory indication is set, and
when not set, is to send read data from far memory to a destination along with a message authentication code (MAC), and
when set, is to encrypt the read data, generate a MAC, and send the encrypted read data and generated MAC to a destination, wherein the fast zero memory indication is to indicate when a read is a first read for a location from the far memory.