CPC H03M 1/662 (2013.01) [H03M 1/74 (2013.01); H03M 1/00 (2013.01); H03M 1/002 (2013.01); H03M 1/0863 (2013.01); H03M 1/66 (2013.01); H03M 1/742 (2013.01)] | 20 Claims |
1. A converter, comprising:
a first input;
a second input; and
a plurality of digital to analog converter (DAC) cells, wherein a DAC cell of the DAC cells comprises a first circuit, a first leg associated with a first output of the DAC cell and a second leg associated with a second output of the DAC cell, wherein the first circuit is configured to provide a return to zero operation during a first time period within a clock cycle, wherein the DAC cell is configured to provide a signal having a data magnitude at a polarity on at least one of the first leg or the second leg during at least a portion of the clock cycle, a first signal at the first input being indicative of the polarity and a second signal at the second input being indicative of the data magnitude.
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