| CPC H03M 1/1245 (2013.01) [H03M 1/129 (2013.01); H03M 1/124 (2013.01); H03M 1/1255 (2013.01); H03M 1/60 (2013.01)] | 5 Claims |
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1. An analog-to-digital converter circuit for digitizing predetermined analog information, the analog-to-digital converter circuit comprising:
a first digitizing unit that comprises:
a first pulse delay circuit comprising a predetermined number of first delay units connected in series, the predetermined number of first delay units being (2n−p), each of n and p being individually a natural number, each first delay unit being configured such that an analog signal having a voltage is inputted thereto, the first pulse delay circuit being configured to transfer a pulse signal therethrough while the pulse signal is delayed by each first delay unit, a delay time of each first delay unit depending on a voltage of the analog signal; and
a first output unit configured to output a first n-bit data value based on the number of first delay units in the first pulse delay circuit through which the pulse signal has passed;
a second digitizing unit that comprises:
a second pulse delay circuit comprising a predetermined number of second delay units connected in series, the predetermined number of second delay units being (2n+p), each second delay unit being configured such that the analog signal is inputted thereto, the second pulse delay circuit being configured to transfer the pulse signal therethrough while the pulse signal is delayed by each second delay unit, a delay time of each second delay unit depending on the voltage of the analog signal; and
a second output unit configured to output a second (n+1)-bit data value based on the number of second delay units in the second pulse delay circuit through which the pulse signal has passed;
a sum output unit configured to calculate the sum of the n-bit data value outputted from the first output unit and the (n+1)-bit data value outputted from the second output unit to accordingly obtain the calculated sum as a digital data value, wherein the second output unit comprises:
an encoder configured to encode, every predetermined period, a value indicative of the number of second delay units in the second pulse delay circuit through which the pulse signal has passed, to accordingly generate, every predetermined period, a digital data value;
a first calculator configured to:
attach, to a newest digital data value, a sign bit as a most significant bit of the newest digital data value to thereby calculate a first digital data value;
attach, to a previous digital data value generated immediately previous to the newest digital data value, the same sign bit as a most significant bit of the previous digital data value to thereby calculate a second digital data value; and
perform subtraction of the second digital data value from the first digital data value to accordingly calculate a third digital data value; and
a second calculator configured to
calculate the sum of a sign bit of the third digital data value as a most significant bit thereof and a second most significant bit of the third digital data value; and
combine a bit selected from the calculated sum of the sign bit and the second most significant bit with the third digital data value from which the sign bit has been eliminated to accordingly generate, as the (n+1)-bit data value, a new digital data value whose most significant bit is the bit selected from the calculated sum of the sign bit and the second most significant bit.
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