| CPC H03K 5/04 (2013.01) [H03K 17/6871 (2013.01)] | 14 Claims |
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1. A structure comprising:
a pad;
a first transistor having a first source region connected to ground, a first drain region, and a first gate, wherein the first transistor is an enhancement mode device;
a capacitor having a first plate connected to the first drain region and a second plate opposite the first plate;
a second transistor having a second source region connected to the first gate, a second drain region connected to the pad, and a second gate connected to the second plate, wherein the second transistor is a depletion mode device; and
a third transistor, a resistor, a voltage clamp, and a fourth transistor connected in parallel between the second gate and ground,
wherein the pad receives a pulse-width modulation signal.
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