US 12,142,805 B2
Nanowire-based integrated via in anodic aluminum oxide layer for CMOS applications
Rhonda Franklin, Minneapolis, MN (US); Yali Zhang, Minneapolis, MN (US); Joseph Um, Minneapolis, MN (US); Bethanie Joyce Hills Stadler, Shoreview, MN (US); and Rashaunda Henderson, Minneapolis, MN (US)
Assigned to Regents of the University of Minnesota, Minneapolis, MN (US); and Board of Regents, The University of Texas System, Austin, TX (US)
Filed by Regents of the University of Minnesota, Minneapolis, MN (US)
Filed on Jun. 4, 2021, as Appl. No. 17/339,267.
Prior Publication US 2022/0393328 A1, Dec. 8, 2022
Int. Cl. H01L 23/66 (2006.01); H01P 3/00 (2006.01); H01P 11/00 (2006.01)
CPC H01P 3/003 (2013.01) [H01L 23/66 (2013.01); H01P 11/001 (2013.01); H01L 2223/6627 (2013.01)] 27 Claims
OG exemplary drawing
 
1. A complementary metal-oxide-semiconductor (CMOS) device, comprising:
a metal oxide layer comprising anodic aluminum oxide (AAO) and one or more nanowires (NW) of an electrically conducting material each formed within a corresponding pore extending through the AAO from a first side of the layer to a second side of the layer opposite the first side;
a first electrically conducting layer disposed on the first side of the metal oxide layer, the first electrically conducting layer being a Cu layer;
a second electrically conducting layer disposed on the second side of the metal oxide layer; and
an adhesion layer between the Cu layer and the metal oxide layer,
wherein the one or more nanowires form a via electrically connecting the first electrically conducting layer and the second electrically conducting layer, and
the AAO has a porosity in a range from 8% to 30%.