US 12,142,700 B2
Solar cell emitter region fabrication with differentiated P-type and N-type architectures and incorporating dotted diffusion
Staffan Westerberg, Sunnyvale, CA (US); and Gabriel Harley, Mountain View, CA (US)
Assigned to Maxeon Solar Pte. Ltd., Singapore (SG)
Filed by Maxeon Solar Pte Ltd., San Jose, CA (US)
Filed on Jan. 11, 2023, as Appl. No. 18/095,769.
Application 15/831,362 is a division of application No. 14/491,045, filed on Sep. 19, 2014, granted, now 9,837,576, issued on Dec. 5, 2017.
Application 18/095,769 is a continuation of application No. 17/068,748, filed on Oct. 12, 2020, granted, now 11,581,443.
Application 17/068,748 is a continuation of application No. 15/831,362, filed on Dec. 4, 2017, granted, now 10,804,415, issued on Oct. 13, 2020.
Prior Publication US 2023/0163225 A1, May 25, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 31/0224 (2006.01); H01L 31/0236 (2006.01); H01L 31/0352 (2006.01); H01L 31/0745 (2012.01); H01L 31/18 (2006.01)
CPC H01L 31/022441 (2013.01) [H01L 31/02363 (2013.01); H01L 31/035281 (2013.01); H01L 31/0745 (2013.01); H01L 31/1872 (2013.01); Y02E 10/50 (2013.01); Y02P 70/50 (2015.11)] 10 Claims
OG exemplary drawing
 
1. A solar cell, comprising:
a substrate having a light-receiving surface and a back surface;
a first dielectric layer on the back surface of the substrate;
a p-type silicon layer on the first dielectric layer;
a second dielectric layer over a plurality of non-continuous regions at the back surface of the substrate;
a plurality of isolated n-type silicon layer features on the second dielectric layer;
a first conductive contact structure electrically connected to the p-type silicon layer;
an insulator layer on the p-type silicon layer, wherein the first conductive contact structure is through the insulator layer, and wherein a portion of the plurality of isolated n-type silicon layer features overlaps the insulator layer but is separated from the first conductive contact structure;
a second conductive contact structure electrically connected to the plurality of isolated n-type silicon layer features, wherein the second conductive contact structure is over the plurality of isolated n-type silicon layer features and a first portion of the insulator layer; and
a third dielectric layer between the p-type silicon layer and at least one of the plurality of isolated n-type silicon layer features, the third dielectric layer having an uppermost surface co-planar with an uppermost surface of the p-type silicon layer.