US 12,142,684 B2
Cut metal gate in memory macro edge and middle strap
Hsin-Wen Su, Hsinchu (TW); Yu-Kuan Lin, Taipei (TW); Chih-Chuan Yang, Hsinchu (TW); Chang-Ta Yang, Hsinchu (TW); and Shih-Hao Lin, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Jul. 26, 2023, as Appl. No. 18/359,034.
Application 18/359,034 is a continuation of application No. 17/352,587, filed on Jun. 21, 2021, granted, now 11,728,432.
Application 17/352,587 is a continuation of application No. 16/441,217, filed on Jun. 14, 2019, granted, now 11,043,595, issued on Jun. 22, 2021.
Prior Publication US 2023/0369496 A1, Nov. 16, 2023
Int. Cl. H01L 29/78 (2006.01); H01L 21/02 (2006.01); H01L 21/762 (2006.01)
CPC H01L 29/785 (2013.01) [H01L 21/02381 (2013.01); H01L 21/02532 (2013.01); H01L 21/02576 (2013.01); H01L 21/02579 (2013.01); H01L 21/76224 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a memory macro, wherein the memory macro includes:
a middle strap area between edges of the memory macro; and
memory bit areas on both sides of the middle strap area,
wherein the memory macro includes:
n-type wells and p-type wells arranged alternately along a first direction with well boundaries between the adjacent n-type and p-type wells, wherein the n-type and the p-type wells extend lengthwise generally along a second direction perpendicular to the first direction and extend continuously through the middle strap area and the memory bit areas; and
a first dielectric layer disposed at the well boundaries in the middle strap area and the memory bit areas, wherein from a top view, the first dielectric layer extends generally along the second direction and fully separates the n-type wells from the p-type wells in the middle strap area, wherein from a cross-sectional view, the first dielectric layer vertically extends into the n-type or the p-type wells.