US 12,142,682 B2
Method of manufacturing semiconductor devices and semiconductor devices
Chandrashekhar Prakash Savant, Hsinchu (TW); Kin Shun Chong, Hsinchu (TW); Tien-Wei Yu, Kaohsiung (TW); Chia-Ming Tsai, Zhubei (TW); and Ming-Te Chen, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jul. 30, 2021, as Appl. No. 17/390,817.
Application 17/390,817 is a division of application No. 16/532,274, filed on Aug. 5, 2019, granted, now 11,081,584.
Claims priority of provisional application 62/753,033, filed on Oct. 30, 2018.
Prior Publication US 2022/0059684 A1, Feb. 24, 2022
Int. Cl. H01L 21/02 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/785 (2013.01) [H01L 21/02153 (2013.01); H01L 21/02186 (2013.01); H01L 21/0228 (2013.01); H01L 21/02362 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor device, comprising:
forming a gate dielectric layer over a channel region;
forming a bilayer cap structure by performing operations comprising:
forming a first layer, which is conductive, over the gate dielectric layer;
forming a second layer over the first layer, wherein the second layer is thinner than the first layer;
performing a first annealing operation after the second layer is formed;
performing a fluorine soaking operation;
forming a third layer over the second layer;
performing a second annealing operation after the third layer is formed;
removing the third layer after the second annealing operation; and
forming a gate electrode layer after the third layer is removed.