| CPC H01L 29/66818 (2013.01) [H01L 21/28132 (2013.01); H01L 29/42392 (2013.01); H01L 29/66439 (2013.01); H01L 29/66545 (2013.01); H01L 29/78696 (2013.01); H01L 29/7848 (2013.01)] | 15 Claims |
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1. A semiconductor device, comprising:
a channel pattern on a substrate, the channel pattern including a plurality of semiconductor patterns spaced apart from each other in a direction perpendicular to a top surface of the substrate;
source/drain patterns spaced apart from each other on the substrate with the channel pattern interposed therebetween;
a gate electrode on a topmost surface of the channel pattern and extending between the semiconductor patterns;
spacer patterns under each of the plurality of semiconductor patterns, wherein each spacer pattern in pairs of the spacer patterns is spaced apart from the other spacer pattern of the pair in a direction parallel to the top surface of the substrate with the gate electrode interposed therebetween; and
gate spacers provided on both sidewalls of the gate electrode, respectively, wherein the spacer patterns are spaced apart from the gate spacers,
wherein each of the spacer patterns is disposed between a corresponding one of the source/drain patterns and the gate electrode,
wherein each of the spacer patterns is in contact with two adjacent semiconductor patterns of the plurality of semiconductor patterns, or in contact with a lowermost semiconductor pattern of the semiconductor patterns and a base pattern underlying the source/drain patterns, and
wherein the spacer patterns include an oxide containing impurities, wherein the impurities include aluminum (Al), gallium (Ga), antimony (Sb), arsenic (As), indium (In), zirconium (Zr), hafnium (Hf), or tantalum (Ta), and wherein each of the spacer patterns has one surface adjacent to the gate electrode, and the one surface of each of the spacer patterns is rounded toward the gate electrode.
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