	US 12,142,666 B2
	Semiconductor device having a gate structure with different lengths between laterally etched spacers
Chun-Yu Kuo, Hsinchu (TW); Shang-Yun Huang, Hsinchu County (TW); and Chih-Yin Kuo, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 28, 2022, as Appl. No. 17/876,158.
Application 17/876,158 is a division of application No. 16/937,389, filed on Jul. 23, 2020, granted, now 11,705,502.
Claims priority of provisional application 62/966,867, filed on Jan. 28, 2020.
Prior Publication US 2022/0376087 A1, Nov. 24, 2022
Int. Cl. H01L 29/78 (2006.01); H01L 21/28 (2006.01); H01L 21/8234 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 21/311 (2006.01)

CPC H01L 29/66545 (2013.01) [H01L 21/28114 (2013.01); H01L 21/823456 (2013.01); H01L 21/823468 (2013.01); H01L 29/42376 (2013.01); H01L 29/6653 (2013.01); H01L 29/6656 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 21/31111 (2013.01); H01L 21/31116 (2013.01)]

20 Claims

1. A semiconductor device, comprising:

a substrate;

a fin on the substrate, the fin comprising a source/drain region;

a pair of first spacers over the substrate, wherein each spacer of the pair of first spacers comprises:

an upper portion having a first length; and

a lower portion under the upper portion and having a second length different from the first length;

a gate structure between the pair of first spacers, wherein the gate structure comprises an upper gate length and a lower gate length that is different from the upper gate length;

a pair of second spacers having substantially straight sidewalls between each of the pair of first spacers and the source/drain region, wherein top surfaces of the pair of second spacers are perpendicular to vertical interfaces between the gate structure and the upper portion of each of the pair of first spacers; and

a liner layer on a side surface of the pair of second spacers and a top surface of the source/drain region.

11. A semiconductor device, comprising:

a channel region on a substrate;

first and second spacers on the channel region;

third and fourth spacers between the first and second spacers, wherein a first horizontal distance between upper portions of the third and fourth spacers is greater than a second horizontal distance between lower portions of the third and fourth spacers, wherein horizontal top surfaces of the first and second spacers are coplanar with top surfaces of the upper portions of the third and fourth spacers, wherein the horizontal top surfaces of the first and second spacers are parallel to top surfaces of the lower portions of the third and fourth spacers;

a gate structure between the third and fourth spacers; and

a liner layer on side surfaces of the first and second spacers, wherein a top surface of the liner layer is perpendicular to an interface between the gate structure and the upper portions of the third and fourth spacers.

16. A semiconductor device, comprising:

a fin structure on a substrate;

first and second spacers on the fin structure;

a gate structure between the first and second spacers, wherein:

the gate structure comprises a lower portion and an upper portion having a lower surface in contact with a first upper surface of the first spacer; and

a first length of the upper portion is greater than a second length of the lower portion;

third and fourth spacers on the fin structure, wherein the first and second spacers are between the third and fourth spacers; and

a liner layer on side surfaces of the third and fourth spacers, wherein a horizontal top surface of the liner layer is coplanar with a second upper surface of the first spacer, and wherein the second upper surface is above the first upper surface.