US 12,142,664 B2
Reducing metal gate overhang by forming a top-wide bottom-narrow dummy gate electrode
Shih Wei Bih, Taichung (TW); Han-Wen Liao, Taichung (TW); Xuan-You Yan, Taichung (TW); Yen-Yu Chen, Taichung (TW); and Chun-Chih Lin, Taipei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsin-Chu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on May 18, 2021, as Appl. No. 17/323,557.
Application 16/050,094 is a division of application No. 15/420,580, filed on Jan. 31, 2017, granted, now 10,446,662, issued on Oct. 15, 2019.
Application 17/323,557 is a continuation of application No. 16/050,094, filed on Jul. 31, 2018, abandoned.
Claims priority of provisional application 62/405,301, filed on Oct. 7, 2016.
Prior Publication US 2021/0280692 A1, Sep. 9, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/66 (2006.01); H01L 21/28 (2006.01); H01L 21/3213 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/423 (2006.01); H01L 29/51 (2006.01); H01L 29/49 (2006.01)
CPC H01L 29/66545 (2013.01) [H01L 21/28114 (2013.01); H01L 21/32135 (2013.01); H01L 21/32137 (2013.01); H01L 27/092 (2013.01); H01L 29/42376 (2013.01); H01L 29/513 (2013.01); H01L 29/517 (2013.01); H01L 21/823828 (2013.01); H01L 21/823842 (2013.01); H01L 29/4966 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a dummy gate electrode layer over a gate dielectric layer;
forming a patterned mask layer over the dummy gate electrode layer;
patterning, using the patterned mask layer as a mask, the dummy gate electrode layer and the gate dielectric layer into a plurality of dummy gate stacks that are spaced apart from one another, wherein each of the dummy gate stacks includes a patterned gate dielectric and a patterned dummy gate electrode, wherein the patterning is performed such that each of the patterned dummy gate electrodes has a top-wide-bottom-narrow profile in a cross-sectional side view, and wherein each of the patterned gate dielectrics has a rectangular profile in the cross-sectional side view, wherein the patterning includes etching, using a fluorine-containing etchant, the dummy gate electrode layer with increasingly stronger lateral etching characteristics, wherein the etching the dummy gate electrode layer includes performing three or more etching steps, wherein each subsequent etching step etches the dummy gate electrode layer at a greater etchant flow rate than a previous etching step, such that a last etching step of the etching is performed with a strongest lateral etching characteristic;
forming gate spacers on sidewalls of the patterned dummy gate electrodes; and
replacing the patterned dummy gate electrodes with metal-containing gate electrodes.