US 12,142,657 B2
Gate structure for multi-gate device and related methods
Kuo-Feng Yu, Hsinchu County (TW); Jiao-Hao Chen, Hsinchu (TW); Chih-Yu Hsu, Hsinchu County (TW); Chih-Wei Lee, Hsinchu (TW); and Chien-Yuan Chen, Taichung (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Apr. 13, 2022, as Appl. No. 17/659,133.
Claims priority of provisional application 63/220,383, filed on Jul. 9, 2021.
Prior Publication US 2023/0012454 A1, Jan. 12, 2023
Int. Cl. H01L 29/423 (2006.01); H01L 21/02 (2006.01); H01L 29/06 (2006.01); H01L 29/40 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/42392 (2013.01) [H01L 21/0259 (2013.01); H01L 29/0665 (2013.01); H01L 29/401 (2013.01); H01L 29/66742 (2013.01); H01L 29/78696 (2013.01); H01L 2029/42388 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a fin extending from a substrate, wherein the fin includes a plurality of semiconductor channel layers; and
a gate dielectric surrounding each of the plurality of semiconductor channel layers;
wherein a first thickness of the gate dielectric disposed on a top surface of a topmost semiconductor channel layer of the plurality of semiconductor channel layers is greater than a second thickness of the gate dielectric disposed on a surface of another semiconductor channel layer disposed beneath the topmost semiconductor channel layer.