US 12,142,655 B2
Transistor gate structures and methods of forming the same
Shih-Yao Lin, New Taipei (TW); Chen-Ping Chen, Toucheng Township (TW); Hsiaowen Lee, Hsinchu (TW); and Chih-Han Lin, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jun. 2, 2021, as Appl. No. 17/336,599.
Claims priority of provisional application 63/059,710, filed on Jul. 31, 2020.
Prior Publication US 2022/0037498 A1, Feb. 3, 2022
Int. Cl. H01L 29/423 (2006.01); H01L 21/02 (2006.01); H01L 21/285 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/45 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/42392 (2013.01) [H01L 21/02532 (2013.01); H01L 21/0259 (2013.01); H01L 21/28518 (2013.01); H01L 21/823807 (2013.01); H01L 21/823814 (2013.01); H01L 21/823864 (2013.01); H01L 21/823871 (2013.01); H01L 21/823878 (2013.01); H01L 27/092 (2013.01); H01L 29/0665 (2013.01); H01L 29/45 (2013.01); H01L 29/66545 (2013.01); H01L 29/66553 (2013.01); H01L 29/66742 (2013.01); H01L 29/78618 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
depositing a dummy gate layer over an isolation region and alternating first nanostructures and second nanostructures, the first nanostructures and the second nanostructures protruding above a top surface of the isolation region;
patterning the dummy gate layer to form a dummy gate on sidewalls of the first nanostructures, sidewalls of the second nanostructures, and the top surface of the isolation region;
forming a protective layer on an upper portion of the dummy gate;
trimming a lower portion of the dummy gate while the protective layer covers the upper portion of the dummy gate; and
replacing the dummy gate and the first nanostructures with a gate structure, the gate structure wrapped around the second nanostructures.