| CPC H01L 29/401 (2013.01) [H01L 21/76897 (2013.01); H01L 29/41733 (2013.01); H01L 29/41791 (2013.01); H01L 29/66742 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 29/78696 (2013.01)] | 20 Claims |

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1. A method, comprising:
forming a source/drain feature adjacent to a semiconductor layer stack disposed over a substrate, the source/drain feature and the semiconductor layer stack disposed along a first plane that extends in a first direction in a top down view;
forming a dummy fin disposed along a second plane in the top view, the second plane parallel to the first plane and extending in the first direction, wherein the dummy fin is adjacent to each of the source/drain feature and the semiconductor layer stack in a second direction in the top down view, the second direction perpendicular to the first direction;
performing an etching process from a backside of the substrate to remove a first portion of the dummy fin adjacent to the source/drain feature, thereby forming a first trench in the dummy fin, wherein the first trench extends from the dummy fin to the source/drain feature;
forming a first dielectric layer in the first trench; and
replacing a second portion of the dummy fin with a source/drain contact.
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