US 12,142,645 B2
Silicon wafer and manufacturing method of the same
Kazuhisa Torigoe, Tokyo (JP); Toshiaki Ono, Tokyo (JP); and Shunya Kawaguchi, Tokyo (JP)
Assigned to SUMCO CORPORATION, Tokyo (JP)
Filed by SUMCO CORPORATION, Tokyo (JP)
Filed on Jun. 5, 2023, as Appl. No. 18/205,886.
Application 18/205,886 is a continuation of application No. 17/225,422, filed on Apr. 8, 2021, granted, now 11,695,048.
Claims priority of application No. 2020-070451 (JP), filed on Apr. 9, 2020.
Prior Publication US 2023/0307505 A1, Sep. 28, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. C30B 33/02 (2006.01); C30B 15/20 (2006.01); C30B 29/06 (2006.01); H01L 21/322 (2006.01); H01L 21/324 (2006.01); H01L 29/32 (2006.01)
CPC H01L 29/32 (2013.01) [C30B 15/203 (2013.01); C30B 29/06 (2013.01); C30B 33/02 (2013.01); H01L 21/3225 (2013.01); H01L 21/324 (2013.01)] 1 Claim
OG exemplary drawing
 
1. A method of making a semiconductor power device comprising
forming circuits on an epitaxial wafer having high gettering capability,
the epitaxial wafer comprising an epitaxial layer, a substrate that is substantially free of crystal-originated-particle defects, and a bulk micro defect (BMD) layer below the epitaxial layer, and a denuded zone between the epitaxial layer and the BMD layer, the BMD layer includes oxygen precipitates wherein a ratio of a first average density of such oxygen precipitates from a first treatment to a second average density of such oxygen precipitates from a second treatment is in a range of about 0.92 to 0.97,
wherein the first treatment includes heating the wafer at about 1000° C. for 16 hours, and the second treatment includes heating the wafer at about 780° C. for 3 hours and then about 1000° C. for 16 hours.